Lateral diffused metal-oxide-semiconductor (LDMOS) devices are widely used for many types of applications, such as high voltage applications. An LDMOS device typically includes a lightly doped drain region to enhance the breakdown voltage.
FIG. 1 illustrates a cross-sectional view of conventional LDMOS devices 2 and 4, which are formed adjacent to each other, with source regions 6 and 8 therebetween. Heavily doped p-type (P+) bulk pick-up region 10 separates source regions 6 and 8. Drain regions 12 are spaced apart from the respective gate electrodes 16 in order to increase drain-gate voltage. Source regions 6 and 8 and drain regions 12 are doped with an n-type impurity. An LDMOS device may include a plurality of legs connected in parallel, and FIG. 1 illustrates one leg of the LDMOS device. Typically gate electrodes 16 of LDMOS devices 2 and 4 are interconnected, and drain regions 12 are interconnected, and thus LDMOS devices 2 and 4 act as a single LDMOS device.
A top view of the structure shown in FIG. 1 is illustrated in FIG. 2. The gate width of gate electrodes 16 is typically long in order for increasing the drive current of the LDMOS device. Source regions 6 and 8 and P+ bulk pick-up region 10 are formed as three parallel strips extending in the gate width direction. The P+ bulk pick-up region 10 adjoins and fully separates source regions 6 and 8. Squares indicated the contacts, which connect metal lines in metallization layers to source regions 6 and 8, P+ bulk pick-up region 10 and drain regions 12.
It is preferred that the conventional LDMOS devices can also act as electrostatic discharge (ESD) devices while at the same time perform the desired LDMOS functionality. However, the electrostatic discharging ability of conventional LDMOS devices is inferior than conventional ESD devices.
Accordingly, the structures and formation methods of LDMOS device need to be changed in order to improve electrostatic discharge abilities of LDMOS devices.